Scalable Task Schedulers for Many-Core Architectures

This thesis develops schedulers for many-cores with different optimization objectives. The proposed schedulers are designed to be scale up as the number of cores in many-cores increase while continuing to provide guarantees on the quality of the schedule

HiMap: Fast and Scalable High-Quality Mapping on CGRA via Hierarchical Abstraction

10.1109/TCAD.2021.3132551IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems1192-119

ChordMap: Automated Mapping of Streaming Applications onto CGRA

10.1109/TCAD.2021.3058313Transactions on Computer-Aided Design of Integrated Circuits and System